This invention relates to communication network apparatus such as is used to link together information handling systems or computers of various types and capabilities and to components of such apparatus. In particular, this invention relates to scalable network processor apparatus and components useful in assembling such apparatus. The description which follows presupposes knowledge of network data communications and switches and routers as used in such communications networks. For assistance in understanding the inventions here described, the following prior disclosure is relevant to the description which follows and is hereby incorporated by reference into this description as fully as if here repeated in full: U.S. Pat. No. 6,404,752 to Allen, Jr., et al., issued Jun. 11, 2002 for “Network Switch Using Network Processor and Methods.”
Typical prior art network processor data flow structures, such as those described in U.S. Pat. No. 6,404,752 incorporated above, include “fixed function placement” structural implementations that are necessarily limiting to overall system functionality and capacity. More specifically, the design of the prior art system structure can generally function in only one predefined frame processing mode. For example, a dataflow structure designed with a “store and dispatch” mode (wherein a packet header must be copied and dispatched for packet processing) is generally desirable for network processor systems that anticipate large accumulations of data in input queue structures.
However, this type of frame processing mode is not optimal where input queues have limited growth potential. A dataflow chip using a “cut and paste” frame processing mode (wherein a frame header may be forwarded immediately to a processing unit while the body of a frame is received in a data store component, and after processing the modified header reconnected to the body in data store) would be more appropriate in this case. Furthermore, for deep packet processing system requirements, a “full dispatch” frame processing mode, also known as “pipelined frame processing” (wherein a full frame is forwarded immediately to a processing unit without being received in data store, and after processing the full modified frame is written in data store) is preferred to optimize data store bandwidth.
And where a “scheduler” structure is provided, the dataflow chip designer must choose either to provide an on-chip internal scheduler structure, which must then accordingly be limited to providing simple scheduling functions, or provide for a port connection to a separate external dedicated hardware structure or an external scheduling software interface when more robust and complex scheduling functions are required or anticipated. Specifically, an embedded ingress scheduler has inherently fixed functionality and limited capacity in terms of data flow quantities. Although simple scheduling functions may be accomplished in prior art network processor devices with embedded hardware or software schedulers, complex scheduling functions typically require connection and interface to an external hardware scheduler structure. And where “scheduler” functions are instead accomplished through software environments, additional processor cycles are required to perform the scheduling functions, resulting in reduced efficiency and system speed.
Therefore, prior dataflow structures do not afford flexibility to the end-user with regard to frame processing modes or scheduler requirements; the resultant dataflow structure is only appropriate for one type of frame processing mode, and/or one type of scheduler structure and, accordingly, system design flexibility or multiple possibilities are greatly reduced or even absent with respect to prior art dataflow structures.
Prior art network processor dataflow structures also typically require limited designated predefined interface structures such as SPI4.2 links, NPF SI switches and NPF LA1 coprocessor interfaces. Accordingly, the number of system configurations possible for any given dataflow structure is constrained by the limited flexibility of its interface structures. Direct connection to external coprocessors, and segmentation and reassembly are typically not supported, and software has limited access to data and data structures.
The aforementioned prior art systems cannot adequately meet the increased demands arising for network processing systems, such as 10 GB per second and higher media speed performance requirements combined with software flexibility. What is needed is a network processor system and method that provides for flexible and multiple alternative frame processing modes to enable efficient data processing, full complex scheduling functions without requiring external components, and superior data transmission capabilities including direct data transmission from external coprocessors, segmentation and data transmission driven by software, and direct access by software to data and data structures, as demanded and required by end-use system requirements. What is also desired is the ability for a dataflow structure to selectively meet multiple frame processing, scheduling and interface requirements as determined and selected by an end-user.